Design Linked Incentive Scheme
Ministry of Electronics and Information Technology, Government of India
SEARCH
Provider Name: CDAC-TVM
IP Type: Hard IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: N/A
Support:N/A
Maturity Level: N/A
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: Hard IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
Semiconductors Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: Datasheets: Interconnect
Semiconductors Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: Datasheets: Interconnect
Semiconductors Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: Datasheets: Interconnect