Semiconductor IP

Semiconductor IP

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1
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Interface/Connectivity IP: USB Host/Device Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
2
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Interface/Connectivity IP: Ethernet Media Access Controller(10/100Mbps)
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
3
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Interface/Connectivity IP: Gigabit Ethernet Media Access Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
4
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Memory Controller IP: Static Memory Controller (SRAM/NOR/eMMC)
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
5
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Memory Controller IP: Direct Memory Access Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
6
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Memory Controller IP: SD Host Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
7
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
System/Peripheral IP: General Purpose Input-Output Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
8
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
System/Peripheral IP: Serial Peripheral Interface Master Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
9
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Processor IP: VEGA ET1031: 32-bit Microprocessor
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
10
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Processor IP: VEGA AS1061: 64-bit Microprocessor
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
11
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Processor IP: VEGA AS1161: 64-bit Microprocessor
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
12
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Processor IP: VEGA AS2161: 64-bit Microprocessor
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
13
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Processor IP: VEGA AS4161: 64-bit Microprocessor
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
14
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Processor IP: VEGA AT1051: 32-bit Microprocessor
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
16
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Basic Function IP: Timer
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
17
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Basic Function IP: UART
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
18
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Basic Function IP: Platform Level Interrupt Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
19
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Basic Function IP: Inter-Integrated Circuit Master Controller
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
20
Provider Name: CDAC-TVM
IP Type: Soft IP
Support:vega[at]cdac[dot]in
Basic Function IP: Pulse Width Modulator
Maturity Level: Silicon Proven
Provided with core: Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: N/A
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
21
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Standard Bus IP: AXI4 Cross-bar Interconnect
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: Datasheets: Interconnect
22
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Processor IP: Chromite Core Generator
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: Datasheets: Chromite, Azurite
23
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Processor IP: Azurite Core Generator
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: Datasheets: Chromite, Azurite
24
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Security IP: AES[128/192/256]
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: N/A
25
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Security IP: SHA[256/512]
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: N/A
26
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Security IP: RSA
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: N/A
27
Provider Name: Incore Semiconductors
IP Type: Soft IP
Support:madhu[at]incoresemi[dot]com
Security IP: ECC
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents: N/A
28
Provider Name: CDAC-Hyderabad
IP Type: Verification IP
Support:anoopkr[at]cdac[dot]in
Verification IP: CCI(Cache Coherrant Interconnect)
Maturity Level: Product
Provided with core: Test Bench
Tested design flows: Simulation & Verification
Technical Documents: User Guides
29
Provider Name: CDAC-Hyderabad
IP Type: Verification IP
Support:anoopkr[at]cdac[dot]in
Verification IP: SD Host Controller
Maturity Level: Product
Provided with core: Test Bench
Tested design flows: Simulation & Verification
Technical Documents: User Guides
30
Provider Name: MosChip Technologies Public Limited
IP Type:Soft IP
Support:sales[at]moschip[dot]com
Analog IP:Power Management
Maturity Level:Prototype
Provided with core: Design Files,Example Designs,Test Bench,Simulation Tool
Tested design flows: Simulation & Verification
Technical Documents: Release Notes & Known Issues,DataSheets,User Guides
31
Provider Name: MosChip Technologies Public Limited
IP Type:Soft IP
Support:sales[at]moschip[dot]com
Analog IP:Clock Management
Maturity Level:Prototype
Provided with core: Design Files,Example Designs,Test Bench,Simulation Tool
Tested design flows: Simulation & Verification
Technical Documents: Release Notes & Known Issues,DataSheets,User Guides
32
Provider Name: MosChip Technologies Public Limited
IP Type:Soft IP
Support:sales[at]moschip[dot]com
Analog IP:LCD Panel Controller
Maturity Level:Prototype
Provided with core: Design Files,Example Designs,Test Bench,Simulation Tool
Tested design flows: Simulation & Verification
Technical Documents: Release Notes & Known Issues,DataSheets,User Guides
33
Provider Name: MosChip Technologies Public Limited
IP Type:Soft IP
Support:sales[at]moschip[dot]com
Analog IP:Temperature Sensor
Maturity Level:Prototype
Provided with core: Design Files,Example Designs,Test Bench,Simulation Tool
Tested design flows: Simulation & Verification
Technical Documents: Release Notes & Known Issues,DataSheets,User Guides
34
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP: PCIe Gen 1 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
35
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP: PCIe Gen 1 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
36
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP: PCIe Gen 2 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
37
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP: PCIe Gen 2 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
38
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 3 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
39
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 3 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
40
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 4 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
41
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 4 EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
42
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 5 EP/RC/ DM
Maturity Level: Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
43
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 5 EP/RC/ DM
Maturity Level: Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
44
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 6 EP/RC/ DM
Maturity Level: Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
45
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 6 EP/RC/ DM
Maturity Level: Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
46
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 7 EP/RC/ DM
Maturity Level: Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
47
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIe Gen 7 EP/RC/ DM
Maturity Level: Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
48
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:CXL V1.x EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
49
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:CXL V1.x EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
50
Provider Name:PRIMESOC Technologies
IP Type: Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:CXL V2.x EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
51
Provider Name:PRIMESOC Technologies
IP Type: Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:CXL V2.x EP/RC/ DM
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
52
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:CXL V3.x EP/RC/ DM
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
53
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:CXL V3.x EP/RC/ DM
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
54
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:UCIe 1.x EP/RC/ DM
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
55
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:UCIe 1.x EP/RC/ DM
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
56
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIE Retimer Gen4/5/6/7
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
57
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIE Retimer Gen4/5/6/7
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
58
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIE Switch G1/2/3/4/5/6/7
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
59
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Interface/Connectivity IP:PCIE Switch G1/2/3/4/5/6/7
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
60
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Audio,Video & Image Processing IP:MIPI CSI TX/RX
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
61
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Audio,Video & Image Processing IP:MIPI CSI TX/RX
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
62
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Audio,Video & Image Processing IP:MIPI DSI TX/RX
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
63
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Audio,Video & Image Processing IP:MIPI DSI TX/RX
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
64
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Standerd Bus IP: AXI4 Memory map
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
65
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Standerd Bus IP:AXI4 Memory map
Maturity Level:Others
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
66
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Standard Bus IP:AXI4 Stream
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
67
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Standard Bus IP:AXI4 Stream
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
68
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Standard Bus IP:APB
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
69
Provider Name:PRIMESOC Technologies
IP Type:Verification IP
Support:ijd[at]primesoctechnologies[dot]com
Standard Bus IP:APB
Maturity Level: Prototype
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance,Supported Device,Tools
Technical Documents: Release Notes & Known Issues, Datasheets, User Guides
70
Provider Name:PRIMESOC Technologies
IP Type:Soft IP
Support:ijd[at]primesoctechnologies[dot]com
Security IP: AES_GCM
Maturity Level: FPGA Prototypes Available
Provided with core: Design Files, Example Designs, Test Bench,Constraint File, Simulation Model
Tested design flows: Design Entry,Simulation & Veriifcation,Synthesis,Benchmarks & Performance
71
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:GNSS FEM: 4 Channel LNA supporting 1/L5/S bands for NavIC, GPS, GLONASS, and BeiDou constellations;
Maturity Level:Silicon Proven
Provided with core:Design Files, Example Designs, Test Bench, Simulation Model
Tested design flows: Schematic → EM → PVT Sim → Layout→Post-Layout
Technical Documents:Release Notes, Datasheet, User Guide, Evalboard Design
72
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:5G Small Cell FEM: 700 MHz to 6 GHz wideband GaAs LNA
Maturity Level:Silicon Proven
Provided with core: Design Files, Example Designs, Test Bench, Simulation Model
Tested design flows: Schematic → EM → PVT Sim → Layout→Post-Layout
Technical Documents: Release Notes, Datasheet, User Guide, Evalboard Design
73
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Sub-1 GHz Transceiver : RFIC 140 MHz to 1 GHz
Maturity Level:Silicon
Provided with core:Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows: Schematic → EM → PVT Sim → Layout→Post-Layout
Technical Documents: Release Notes, Datasheet, User Guide, Evalboard Design
74
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:GNSS RFIC: RFIC 1.175 GHz to 1.575 GHz
Maturity Level:Schematic
Provided with core: Target Specification
Tested design flows: NA
Technical Documents: NA
75
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ku LNA (13.75 -14.5GHz)
Maturity Level:Silicon Proven
Provided with core:Target Specification
Tested design flows: NA
Technical Documents: NA
76
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ka LNA (27 -31GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
77
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ku PA 100mW (13.75 -14.5GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
78
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ka PA 100mW (27 -31GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
79
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ku PA 7W (10.9 -12.7GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
80
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ka PA 7W (17 -21.2GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
81
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ku PA 10W (10.9 -12.7GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
82
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP:Leo Satcomm RF Component: Ka PA 10W (17 -21.2GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
83
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: Leo Satcomm RF Component: Ku PA 25W (10.9 -12.7GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
84
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: Leo Satcomm RF Component: Ka PA 25W (17 -21.2GHz)
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
85
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: Mixer S/Ku/Ka
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
86
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: PLL IP: 0.7-1.5G, low power PLL for display driver MCU
Maturity Level:Layout
Provided with core:Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows:Schematic → EM → PVT Sim → Layout→Post-Layout
Technical Documents:Release Notes, Datasheet, User Guide
87
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: PLL IP: Low phase noise PLL for GNSS bands
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
88
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: PLL IP: Low Phase noise wideband PLL for SubGHz
Maturity Level:Silicon
Provided with core:Design Files, Example Designs, Test Bench, Simulation Model
Tested design flows:Schematic → EM → PVT Sim → Layout→Post-Layout
Technical Documents:Release Notes, Datasheet
89
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: ADC IP: 10bit, 10 Mhz, 20MSPS
Maturity Level:Silicon
Provided with core:Design Files, Example Designs, Test Bench, Simulation Model
Tested design flows:Schematic → EM → PVT Sim → Layout→Post-Layout
Technical Documents:Release Notes, Datasheet
90
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: ADC IP: 2bit, 10 Mhz, 20MSPS
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
91
Provider Name: Silizium Circuits
IP Type:Hard IP
Support:info[at]siliziumcircuits[dot]
Analog IP: ADC IP: 14bit, 2MSPS
Maturity Level:Schematic
Provided with core:Target Specification
Tested design flows:NA
Technical Documents:NA
93
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in; harsh[at]scl[dot]gov[dot]in; munish[at]scl[dot]gov[dot]in;ajay_k[at]scl[dot]gov[dot]in
Interface/Connectivity IP: LVDS Receiver1 (400 Mbps)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Simulation Datasheet
94
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; munish[at]scl[dot]gov[dot]in;ajay[at]scl[dot]gov[dot]in
Interface/Connectivity IP: LVDS Transmitter1 (400 Mbps)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents:Simulation Datasheet
95
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; anuj[at]scl[dot]gov[dot]in;basra[at]scl[dot]gov[dot]in
Memory IP: Standard 4LM SPRAM Cuts (17)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files and All EDA views
Tested design flows: Simulation, Physical Verification
Technical Documents: Generic Datasheets
96
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; anuj[at]scl[dot]gov[dot]in;basra[at]scl[dot]gov[dot]in
Memory IP: Standard 6LM SPRAM Cuts (20)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files and All EDA views
Tested design flows: Simulation, Physical Verification
Technical Documents: Generic Datasheets
97
Provider Name: SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; anuj[at]scl[dot]gov[dot]in;basra[at]scl[dot]gov[dot]in
Memory IP: Standard 4LM DPRAM Cuts (20)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files and All EDA views
Tested design flows: Simulation, Physical Verification
Technical Documents: Generic Datasheets
98
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; anuj[at]scl[dot]gov[dot]in;basra[at]scl[dot]gov[dot]in
Memory IP: Standard 6LM DPRAM Cuts (20)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files and All EDA views
Tested design flows: Simulation, Physical Verification
Technical Documents: Generic Datasheets
99
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; asim[at]scl[dot]gov[dot]in;manojkr[at]scl[dot]gov[dot]in
Analog IP: CMOS Temperature Sensor1 (3.3V PowerSupply,4mV/°C,1.25V typical output)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Simulation Datasheet
100
Provider Name: SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; asim[at]scl[dot]gov[dot]in;manojkr[at]scl[dot]gov[dot]in
Analog IP: CMOS Temperature Sensor2 (3.3V Power Supply,11mV/°C, 750V typical output)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Datasheet
101
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; asim[at]sc[dot]gov[dot]in;rajiv[dot]bhatia[at]scl[dot]gov[dot]in;manojkr[at]scl[dot]gov[dot]in
Analog IP: Temperature Compensated Oscillator (128 KHz)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Simulation Datasheet
102
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; asim[at]scl[dot]gov[dot]in
Analog IP: Current Feedback Instrumentation Amplifier (Programmable gain upto 32 V/V)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents:Datasheet
103
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; sehgal[at]scl[dot]gov[dot]in;anil[at]scl[dot]gov[dot]in
Analog IP: LDO1 (1.8V/12mA)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Datasheet
104
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; sehgal[at]scl[dot]gov[dot]in;anil[at]scl[dot]gov[dot]in
Analog IP: LDO2 (1.8V/150mA)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Datasheet
105
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; sehgal[at]scl[dot]gov[dot]in;anil[at]scl[dot]gov[dot]in
Analog IP: Voltage Reference (3.3V Power Supply, 1.17 V)
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Simulation Datasheet
106
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; sehgal[at]scl[dot]gov[dot]in;anil[at]scl[dot]gov[dot]in
Security IP: Integer Phase Locked Loop (PLL) (Clock generation up to 1.2 GHz)
Maturity Level: Silicon Proven
Provided with core: Design Files (netlist & gds)
Tested design flows: Physical Verification
Technical Documents: Datasheet
107
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; ashutosh[at]scl[dot]gov[dot]in;averma[at]scl[dot]gov[dot]in
Analog IP: POR1
Maturity Level: Silicon Proven(In other Products)
Provided with core: Design Files (netlist & gds)
Tested design flows: FE & BE Design, Simulation, Physical Verification
Technical Documents: Simulation Datasheet
108
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; sunilk[at]scl[dot]gov[dot]in
Sysetm/Peripheral IP: SPI Controller
Maturity Level: Silicon Proven
Provided with core: Design Files (RTL, constraint file)
Tested design flows: FE & BE Design, Synthesis, Simulation, Physical Verification
Technical Documents: Datasheet
109
Provider Name:SCL
IP Type:Hard IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in;pooja[at]scl[dot]gov[dot]in
Processor IP: 8-Bit Microcontroller
Maturity Level: Silicon Proven
Provided with core: Design Files (RTL, constraint file)
Tested design flows: FE & BE Design, Synthesis, Simulation, Physical Verification
Technical Documents: Datasheet
110
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: PCIe Gen2
Maturity Level: Silicon Proven
Provided with core:Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+, 55nm TSMC, 55LP, TSMC 65G
111
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: PCIe Gen3/2/1
Maturity Level: Silicon Proven
Provided with core:Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, Samsung 28SLP, 55LP, TSMC 65G
112
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: PCIe Gen4/3/2/1
Maturity Level: Others (CAD proven)
Provided with core:Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, GF 28SLP, Samsung 28SLP
113
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: PCIe Gen5/4/3/2/1 *
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
114
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: USB 3.1/3.0
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+, GF 28SLP
115
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: USB 3.2 GEN2 single lane
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+, 55LP, TSMC 65G
116
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: USB 3.2 Gen2 Quadlane
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+
117
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: USB 3.2 Gen2 2x2
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+, 55LP, TSMC 65G
118
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Serdes 10G *
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, 55LP, TSMC 65G
119
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Serdes 16G
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
120
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Ethernet_56G
Maturity Level: Others (under development)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm
121
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Ethernet_10G
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, TSMC 65G
122
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Ethernet 1G Base T
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
123
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Ethernet 1G Base T
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, TSMC 22nm
124
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Etherrnet 10G Base T
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+
125
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: Ethernet 10G Base T
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+
126
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Interface/Connectivity IP: MIPI MPHY_Gear4
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+, 55nm TSMC
127
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL 32 gbps
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
128
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_16GHz
Maturity Level: Others (CAD proven)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
129
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_10_GHz
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, 55LP, TSMC 65G
130
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_8_GHz
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, TSMC 65G
131
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_5_GHz
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, GF 28SLP, Samsung 28SLP, 55LP, TSMC 65G
132
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_2.5_GHz
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, TSMC 65G
133
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_4GHz
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, GF 28SLP, Samsung 28SLP
134
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: PLL_6_8GHz
Maturity Level: Others (developed)
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, GF 28SLP
135
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: CDR_16G
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
136
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: CDR_10G
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, GF 28SLP, Samsung 28SLP, 55LP, TSMC 65G
137
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: CDR_8G
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, Samsung 28SLP, TSMC 65G
138
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: CDR_5G
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, Samsung 28SLP, 55LP, TSMC 65G
139
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: BGR_0.9V
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+
140
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: BGR_1.0V
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55nm TSMC, GF 28SLP, Samsung 28SLP
141
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: BGR_1.2V
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 12nm, 28nm TSMC HPC/+, 55LP, TSMC 65G
142
Provider Name:Terminus Circuits
IP Type:Hard IP
Support: sales[at]terminuscircuits[dot]com
Analog IP: BGR_1.8V
Maturity Level: Silicon Proven
Provided with core: Standard IP deliverable: flat encrypted GDS,LVS compatible CDL, LEF, Inegraion guideline
Tested design flows: All our licensed IP are silicon proven at our end or at customer site
Technical Documents: Datasheets/Product briefs
Process Nodes Available: 28nm TSMC HPC/+
143
Provider Name:SCL
IP Type:Soft IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in; sunilk[at]scl[dot]gov[dot]in
Sysetm/Peripheral IP: SPI Controller
Maturity Level: Silicon Proven
Provided with core: Design Files (RTL, constraint file)
Tested design flows: FE & BE Design, Synthesis, Simulation, Physical Verification
Technical Documents: Datasheet
144
Provider Name:SCL
IP Type:Soft IP
Support: shilpa[at]scl[dot]gov[dot]in;harsh[at]scl[dot]gov[dot]in;pooja[at]scl[dot]gov[dot]in
Processor IP: 8-Bit Microcontroller
Maturity Level: Silicon Proven
Provided with core: Design Files (RTL, constraint file)
Tested design flows: FE & BE Design, Synthesis, Simulation, Physical Verification
Technical Documents: Datasheet

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