Design Linked Incentive Scheme
Ministry of Electronics and Information Technology, Government of India
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(current)
Provider Name
CDAC
InCore SEMI
IP Type
Hard IP
Soft IP
Firm IP
Verification IP
Others
Maturity Level
Silicon Proven
Silicon
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IP Categories
Memory Controller IP
Static Memory Controller (SRAM/NOR/eMMC)
Direct Memory Access Controller
SDRAM Controller
SD Host Controller
Analog IP
System/Peripheral IP
Display Controller
General Purpose Input-Output Controller
Serial Peripheral Interface Master Controller
Audio,Video & Image Processing IP
Automotive & Industrial IP
Standard Bus IP
AXI Bus Interconnect
AXI to APB Bus converter
AXI4 Cross-bar Interconnect
Processor IP
VEGA ET1031: 32-bit Microprocessor
VEGA AS1061: 64-bit Microprocessor
VEGA AS1161: 64-bit Microprocessor
VEGA AS2161: 64-bit Microprocessor
VEGA AS4161: 64-bit Microprocessor
Chromite Core Generator
Azurite Core Generator
Debug IP
RISC-V Debug module
Security IP
AES[128/192/256]
SHA[256/512]
RSA
ECC
Basic Function IP
Manchester Encoder Decoder core
Timer
UART
Platform Level Interrupt Controller
Watch Dog Timer
Inter-Integrated Circuit Master Controller
Quad SPI
Pulse Width Modulator
Others
Provider Name:
CDAC-TVM
IP Type:
Hard IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
Soft IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
N/A
Support:
N/A
Maturity Level:
N/A
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
Hard IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
Soft IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
Soft IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
Soft IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Provider Name:
CDAC-TVM
IP Type:
Soft IP
Support:
vega[at]cdac[dot]in
Maturity Level:
Silicon Proven
Provided with core:
Design Files, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
N/A
Technical Documents:
Release Notes & Known Issues, Datasheets, User Guides
Semiconductors
Provider Name:
Incore Semiconductors
IP Type:
Soft IP
Support:
madhu[at]incoresemi[dot]com
Maturity Level:
FPGA Prototypes Available
Provided with core:
Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows:
Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents:
Datasheets: Interconnect
Semiconductors
Provider Name:
Incore Semiconductors
IP Type:
Soft IP
Support:
madhu[at]incoresemi[dot]com
Maturity Level:
FPGA Prototypes Available
Provided with core:
Design Files, Example Designs, Test Bench, Constraint File, Simulation Model, Supported Drivers
Tested design flows:
Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents:
Datasheets: Interconnect
Semiconductors
Provider Name:
Incore Semiconductors
IP Type:
Soft IP
Support:
madhu[at]incoresemi[dot]com
Maturity Level:
FPGA Prototypes Available
Provided with core:
Design Files, Example Designs, Test Bench, Constraint File, Simulation Model
Tested design flows:
Design Entry, Simulation & Verification, Synthesis, Benchmarks & Performance
Technical Documents:
Datasheets: Interconnect